Integrated circuits are chemically and physically integrated into a substrate, such as a silicon wafer, by patterning regions in the substrate and by patterning layers on the substrate. These regions and layers can be conductive for conductor and resistor fabrication. They can also be of different conductivity types, which is essential for transistor and diode fabrication. When fabricating the various circuit components or devices within the substrate, it becomes necessary to isolate devices from one another.
A variety of techniques have been developed for electrically isolating devices formed within a bulk substrate in integrated circuit fabrication. One common isolation technique developed is termed LOCOS isolation for LOCal Oxidation of Silicon, which involves the formation of a semi-recessed oxide in the nonactive (or field) areas of a substrate. The principal LOCOS approach selectively grows oxide over desired field regions. This is accomplished by covering active regions with a thin layer of silicon nitride that prevents oxidation from occurring therebeneath. The nitride layer is patterned and etched to upwardly expose those silicon areas within which field oxide is desired to be grown. The wafer is thereafter subjected to oxidizing conditions. The oxide grows where there is no masking nitride. However at the edges of the nitride masking, some oxidant does diffuses laterally.
This causes the oxide to grow under and lift the nitride edges. The shape of the oxide at the nitride edges is that of a slowly tapering oxide wedge that merges into an underlying pad oxide layer, and has been termed as a bird's beak. The bird's beak is a lateral extension of the field oxide into the active areas of the devices. One drawback of such an isolation technique is that the bird beak results in field oxide being produced which has greater lateral dimensions than the minimum photo feature size utilized to create the mask opening in the nitride.
Accordingly as device geometry reached submicron size, conventional LOCOS isolation technologies reach the limits of their effectiveness, and alternate isolation processes for CMOS and bipolar technologies were needed. One such technique includes trench isolation. Here, filled isolated trenches are provided vertically into the substrate which separate or isolate electric devices on either side of the trench. This invention concerns processing methods for forming such substrate isolation trenches.
One such prior art isolation trench technique and problems associated therewith are described with reference to FIGS. 1-5. FIG. 1 illustrates a semiconductor substrate 10 comprised of a bulk substrate 12, a thin layer of pad oxide 14 and a layer of photoresist 16. Photoresist layer 16 is patterned to produce a contact opening 20 through which a trench is to be formed.
Referring to FIG. 2, pad oxide layer 14 and bulk substrate 12 are etched as indicated to produce a cavity or trench 22.
Referring to FIG. 3, a layer 24 of SiO.sub.2 is grown within trench 22. An additional isolation implant 26 can also be provided at the base of trench 22, as shown. For example where bulk substrate 12 comprises p- silicon where n-channel devices will be provided therein, implant 26 could be a p+ implant to provide further electrical isolation effect between circuit components to be developed on opposing sides of trench 22. Such implant would typically be provided before the removal of mask layer 16 shown in FIG. 1.
Referring to FIG. 4, a layer 28 of trench filling material is provided atop the wafer to fill trench 22. The material of layer 28 could be polysilicon or oxide, or some other bulk, mass of material to fill the volume of trench 22. It need not necessarily be an insulating material since oxide layer 26 provides an electrically isolating effect across the lateral extent of trench 22. Such layer is typically conformally deposited creating the illustrated depression or "V" 30 as illustrated.
Referring to FIG. 5, layer 28 is subjected to a suitable etch to remove such material to the point of leaving trench 22 substantially filled. However, as shown, and unfortunately, the conformal depositing nature of layer 28 typically results in the "V" 30a still remaining after the etch, which is undesirable.
It would be desirable to improve upon these and other techniques associated with formation of substrate isolation trenches.